Search - uart code in verilog

[VHDL-FPGA-Verilog] S6_VGA_change

Description: verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，-Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off,
Platform: | Size: 2572288 | Author: 李晨 | Hits:

[VHDL-FPGA-Verilog] uart_51

Description: 符合8051协议规范的UART的Verilog源代码.该压缩包是一个modelsim的工程.-8051 agreement in line with the norms of the Verilog source code UART. The Compression Pack is a ModelSim project.
Platform: | Size: 41984 | Author: 王亮 | Hits:

[Com Port] uart

Description: this a Uart source code using Verilog.
Platform: | Size: 10240 | Author: Daniel Zhang | Hits:

[Com Port] uart(Verilog)

Description: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Platform: | Size: 10240 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] fpga_uartrw

Description: FPGA的uart控制器的verilog源程序，在cyclone II EP2C8Q208上调试运行成功-FPGA s UART controller Verilog source code, in cyclone II EP2C8Q208 debugging run successfully
Platform: | Size: 55296 | Author: 蒋斌斌 | Hits:

[VHDL-FPGA-Verilog] UART_for_FPGArar

Description: it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]
Platform: | Size: 5120 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA开发的串口通信的程序，代码是用verilog编写的，希望对大家有用！-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
Platform: | Size: 267264 | Author: 郭富民 | Hits:

[Other] uart_rx

Description: Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
Platform: | Size: 1024 | Author: hassan | Hits:

[VHDL-FPGA-Verilog] sim_uart

Description: uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1，无校验位；代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through
Platform: | Size: 2048 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] FPGA_UART

Description: 用Verilog语言实现的FPGA UART独立收发模块思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
Platform: | Size: 3072 | Author: 朱强光 | Hits:

[VHDL-FPGA-Verilog] UART_send

Description: uart的verilog代码，在赛灵思的spartan 3E上经过验证，电路有一定的质量。-The verilog uart code, in the spirit of the best Spartan 3 E after verification, circuit has certain quality.
Platform: | Size: 1695744 | Author: skjin | Hits:

[VHDL-FPGA-Verilog] UART_acpt

Description: The verilog uart code, in the spirit uart的verilog代码，在赛灵思的spartan 3E上经过验证，电路有一定的质量。-The verilog uart code, in the spirit of the best Spartan 3 E after verification, circuit has certain quality.
Platform: | Size: 408576 | Author: skjin | Hits:

[VHDL-FPGA-Verilog] Uart

Description: UART source code in verilog
Platform: | Size: 1024 | Author: Sweetu | Hits:

[Other] 1.UART

Description: 该代码主要实现UART的串行通信，针对的是RS232芯片，同时包含了verilog和VHDL编写的程序-The code UART serial communication, RS232 chip, also contains a program written in verilog and VHDL
Platform: | Size: 1501184 | Author: mingbo | Hits:

[Software Engineering] UART

Description: 基于ISE 用verilog编写的uart串口通信源码-Based on the ISE written in verilog uart serial communication source code
Platform: | Size: 1024 | Author: 祁伟 | Hits:

[VHDL-FPGA-Verilog] UART-Verilog-source

Description: Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test
Platform: | Size: 3072 | Author: charley | Hits:

[VHDL-FPGA-Verilog] UART

Description: Verilog HDL编写的串口程序实例，很详细好用的参考代码。针对Xilinx FPGA开发板，在Xilinx ISE编译调试成功，串口开发的经典例程。-Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a serial port development of classic routines.
Platform: | Size: 219136 | Author: 韩建平 | Hits:

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[VHDL-FPGA-Verilog] S6_VGA_change

[VHDL-FPGA-Verilog] uart_51

[Com Port] uart

[Com Port] uart(Verilog)

[VHDL-FPGA-Verilog] fpga_uartrw

[VHDL-FPGA-Verilog] UART_for_FPGArar

[VHDL-FPGA-Verilog] UART

[Other] uart_rx

[VHDL-FPGA-Verilog] sim_uart

[VHDL-FPGA-Verilog] FPGA_UART

[VHDL-FPGA-Verilog] UART_send

[VHDL-FPGA-Verilog] UART_acpt

[VHDL-FPGA-Verilog] Uart

[Other] 1.UART

[Software Engineering] UART

[VHDL-FPGA-Verilog] UART-Verilog-source

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] rs232

[VHDL-FPGA-Verilog] LIFO_Spartan3

[VHDL-FPGA-Verilog] uart

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